The present invention relates to integrated circuit electronic devices, and, more particularly, to microcomputers, microcontrollers, and microprocessors.
Microprocessor Performance
The demand for ever higher performance from computers generally, and microprocessors and microcontrollers in particular, has led to various enhancements including higher clock rates and simpler instruction sets. However, higher clock rates imply less time for instructions including multiple steps which are to be performed in a single machine cycle. In particular, addressing modes such as register indirect addressing still require two memory fetches be made: the first fetch retrieves the contents of the addressing register and the second fetch uses these contents as the address for a data fetch. And two fetches for a single byte instruction will require two machine cycles for the instruction execution unless the machine cycle is fairly long and slow. Thus a problem exists for improving performance of microprocessors and microcontrollers in connection with register indirect addressing.
One approach to multiple step instructions subdivides the clock cycle so that both rising and falling edges of the clock can be used. However, the duty cycle of a clock cannot be relied on as remaining stable as operating conditions such as power supply voltage and temperature vary. Further, use of both rising and falling clock edges only provides a single extra timing edge. A more accurate and flexible partitioning of the, clock period to provide more timing edges than just the half period permits use of slower memories with a microcontroller because the portion of the clock period permitted for memory access can be adjusted to accommodate the memory. U.S. Pat. No. 4,893,271 has a phase-locked loop to selectively multiply the crystal oscillator frequency to use as the microprocessor clock and thereby effectively achieve a partitioning of the crystal oscillator period. However, this does not provide a true internal partitioning of the clock period. Thus a problem exists for accurately partitioning the clock period of a microcontroller or microprocessor.
Further problems which arise with higher clock rates for microcontrollers and microprocessors include ringing in output drivers while driving capacitive loads due to the inductance of bond wires. The larger current needed when an output driver must charge up a large load capacitance in a shorter clock period implies overshoot and ringing for a small load capacitance. Thus a problem exists to reduce ringing in output drivers.
Another problem of high performance microprocessors and microcontrollers arises from the recovery time of the crystal oscillator clock following an interrupt-generated restart from a stop mode. A crystal oscillator typically takes a couple of milliseconds to recover and prevents immediate execution of instructions in response to the interrupt.
Microprocessors and microcontrollers typically have a watchdog timer which will generate a system reset signal unless program execution continually resets the watchdog timer. Such a watchdog will permit a system to escape from a lockup condition by the reset. However, some systems do not require a reset circuit, and the watchdog will not be utilized.
Features
The present invention provides microprocessors and microcontrollers with high performance through (1) register indirect addressing through registers which have their contents available on a bus multiplexed to the memory address decoders, (2) clock partitioning through an adjustable delay line with feedback loop control to accurately partition the clock period, (3) multiple stage output drivers for current control, (4) a noncrystal oscillator clock to provide clocking during startup intervals when the crystal oscillator has not yet stabilized, and (5) a watchdog interrupt combined with the watchdog reset to provide uses for the watchdog in systems without resets.